1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to a semiconductor memory device equipped with a timing control circuit that simulates signal delay.
2. Description of the Related Art
In order to increase the operation speed of semiconductor memory devices, diligent timing control becomes necessary regarding the operations of semiconductor memory devices. When an attempt is made to manufacture increasingly fine structures in order to increase the circuit density of semiconductor memory devices, an increase in product variation may ensue. If such product variation exists, it is not easy to attend to diligent timing control.
In conventional technologies, timing control signals that define the operation timing of internal circuitry are generated from external signals by use of delay circuits or the like. The timing of timing control signals generated in this manner may deviate if parasitic load capacitance or resistance associated with wires exhibits variation due to the product variation. Timing settings must thus be made with a sufficient margin by taking into account such deviations, which is a factor that hinders effort toward the attainment of high-speed semiconductor memory devices.
In order to obviate this problem, some types of semiconductor memory devices simulate signal delay inside the semiconductor memory devices, thereby generate accurate timing control signals. Such timing control circuit is called a self-timing circuit. For example, the path that incurs the longest timing delay at the time of memory access is taken into consideration, and a circuit is provided to simulate the signal delay along this path, thereby generating timing control signals for defining the operation timing of internal circuitry. In this method, the timing control signal has timing that emulates actual memory access, so that timing deviation caused by the product variation can be suppressed to some extent.
The path that incurs the longest timing delay used for generating the timing control signal is a path that is farthest away from the input/output circuit, and that accesses the memory cell that is farthest away from the word decoder.
FIG. 1 is an illustrative drawing for explaining timing compensation when the path farthest away from an input/output circuit and a word decoder is used.
The semiconductor memory device of FIG. 1 includes a control circuit 11, a decoder circuit 12, a memory cell array 13, a read-write amplifier 14, a dummy word decoder 15, a dummy word line 16, a dummy memory cell 17, and a dummy bit line 18. At the time of an actual data read operation, the decoder circuit 12 selectively activates a word line of the memory cell array 13 in response to a clock signal CK and an address signal ADDRESS supplied to the control circuit 11 from an exterior of the device, thereby supplying a read signal to a memory cell 19. A signal path along which the read signal propagates is shown as signal paths P1, P2 and P3. The memory cell 19 that is accessed in the memory cell array 13 is shown as a cell that is farthest away from the control circuit 11. Data read from the memory cell 19 is supplied to the read-write amplifier 14 through a path p4 that corresponds to bit lines of the memory cell array 13. The data retrieval paths P1, P2, P3, and P4 together form the path that incurs the longest delay for a data read operation, and is thus a critical path that is most critical in terms of timing.
In the meantime, the dummy word decoder 15 activates the dummy word line 16 based on the clock signal CK and the address signal ADDRESS supplied to the control circuit 11 from the exterior of the device, thereby supplying a read signal to the dummy memory cell 17. A path along which this read signal propagates is shown as paths P1, P6, and P7. A dummy-memory-cell signal read from the dummy memory cell 17 is supplied through the dummy bit line 18 to the control circuit 11. Based on this dummy-memory-cell signal, the control circuit 11 supplies a sense amplifier activation signal to the read-write amplifier 14 so as to amplify the real data that is read. The path along which the dummy-memory-cell signal and the sense amplifier activation signal propagate is shown as paths P8, P9, and P5.
In this manner, the real data that is read through the data retrieval paths P1, P2, P3, and P4 is amplified by the read-write amplifier 14 and then output to the exterior of the device through a path P10. The path along which the dummy-memory-cell signal is retrieved has a timing delay longer than that of the critical path that has the longest timing delay in the memory cell array 13. This insures that the reading of data along the critical path is properly performed. In this manner, the self-timing circuit generates a timing control signal (i.e., the sense amplifier activation signal) that simulates real memory access, thereby canceling a timing deviation caused by product variation.
In the configuration described above, the dummy memory cell 17 is provided farther away than the memory cell 19 that is farthest away from the control circuit 11. Accordingly, the load of driving the dummy word decoder 15, the dummy word line 16, the dummy bit line 18, etc., is greater than the maximum load that can be incurred when reading data from the memory cell array 13. This gives rise to a problem in that power consumption by the self-timing circuit increases. The power consumption by the self-timing circuit is not an ignorable size in memory devices for which a reduction of power consumption is a primary consideration.
Accordingly, there is a need for a semiconductor memory device that is provided with a self-timing circuit for simulating signal delay so as to insure stability against product variation where the self-timing circuit incurs relatively small power consumption.